Mon Tue Wed Thu Fri
1/6
 
1/7
 
1/8
1/9
 
1/10
 
1/13
1/14
 
1/15
1/16
 
1/17
Lab1 due
1/20
MLK Day
1/21
Add/drop ends
1/22
1/23
 
1/24
 
1/27
Memory and Addresses
1/28
Late drop ends
1/29
Control Flow
1/30
 
1/31
Lab2 due
2/3
Arrays
2/4
 
2/5
Functions
2/6
 
2/7
Lab3 due
2/10
The Stack and Saved Registers
2/11
 
2/12
Exam 1 Review
2/13
 
2/14
Lab4 due
2/17
Exam 1
2/18
 
2/19
CPU Intro
2/20
 
2/21
 
2/24
Schematics and Gates
2/25
 
2/26
Addition and Overflow
2/27
 
2/28
Proj1 due
3/3
Spring Break
3/4
 
3/5
 
3/6
 
3/7
 
3/10
Overflow, Multiplexers, and Bitwise Operations
3/11
WD & EC due**
3/12
Shifting and Bitsets
3/13
 
3/14
Lab5 due
3/17
Floating-point Numbers and Bitfields
3/18
 
3/19
Sequential Logic, Registers, and Clocking
3/20
 
3/21
Lab6 due
3/24
FSMs and Multiplication
3/25
 
3/26
Multiplication and Division
3/27
 
3/28
Lab7 due
3/31
The Register File, ALU, and Memory
4/1
 
4/2
The PC and Interconnect
4/3
 
4/4
Lab8 due
4/7
The Control
4/8
 
4/9
Performance
4/10
 
4/11
 
4/14
Multicycle and Microcode
4/15
 
4/16
Pipelining, Caching, and Superscalar
4/17
 
4/18
Proj2 due
4/21
Exam 2 Review
4/22
 
4/23
 
4/24
MW Exam2*
4/25
 
4/28
 
4/29
TH Exam2*
4/30
 
5/1
 
5/2
 

*Final exam times: final exam days/times are randomly selected by the university based on when your lecture section meets. Rooms have not yet been assigned but I will put them here when they are.

**WD = withdrawals, EC = final exam conflicts